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^lwnmnoa= ezbuck? 3a simple buck regulator april 2006 april 2006 www.aosmd.com page 1 of 17 general description the aoz1012d is a high efficiency, simple to use, 3a buck regulator. the aoz1012d work s from a 4.5v to 16v input voltage range, and provides up to 3a of continuous output current with an output voltage adjustable down to 0.8v. the aoz1012d comes in 4x5 dfn-8 packages and is rated over a -40c to +85c ambient temperature range. features ? 4.5v to 16v operating input voltage range ? 50 m ? internal pfet switch for high efficiency: up to 95% ? internal schottky diode ? internal soft start ? output voltage adjustable to 0.8v ? 3a continuous output current ? fixed 500khz pwm operation ? cycle-by-cycle current limit ? short-circuit protection ? thermal shutdown ? small size dfn-8 packages applications ? point of load dc/dc conversion ? pcie graphics cards ? set top boxes ? dvd drives and hdd ? lcd panels ? cable modems ? telecom/networking/datacom equipment typical application l1 c2 vout aoz1012d c1 lx vin fb gnd comp en 22uf 47uf 3.3uh from upc r c c c r1 r2 +3.3v output @3a vin figure 1. 3.3v/3a buck down regulator
^lwnmnoa april 2006 www.aosmd.com page 2 of 17 ordering information part number ambient temperature range package environmental AOZ1012DI -40c to +85c dfn-8 rohs compliant pin configuration 1 2 3 4 8 7 6 5 vin agnd comp lx lx en fb pgnd lx agnd 4x5 dfn pin description pin number pin name pin function 1 vin supply voltage input. when vi n rises above the uvlo threshold the device starts up. 2 pgnd power ground. electrically needs to be connected to agnd. 3 agnd reference connection for controlle r section. also used as thermal connection for controller section. electrically needs to be connected to pgnd. 4 fb the fb pin is used to determine the output voltage via a resistor divider between the output and gnd. 5 comp external loop compensation pin. 6 en the enable pin is active high. connect en pin to vin if not used. do not leave the en pin floating. 7,8 lx pwm output connection to inductor. thermal connection for output stage. absolute maximum ratings (1) recommend operating ratings (2) parameter units parameter units supply voltage (v in ) 18v supply voltage (v in ) 4.5v to 16v lx to agnd -0.7v to v in +0.3v output voltage range 0.8v to v in en to agnd -0.3v to v in +0.3v ambient temperature (t a ) -40c to +85c fb to agnd -0.3v to 6v comp to agnd -0.3v to 6v package thermal resistance dfn-8 ( ja ) 53 c/w pgnd to agnd -0.3v to +0.3v junction temperature (t j ) +150c storage temperature (t s ) -65c to +150c
^lwnmnoa april 2006 www.aosmd.com page 3 of 17 electrical characteristics t a = 25c, v in = v en = 12v, v out = 3.3v unless otherwise specified (4) . parameter symbol conditions min typ max units supply voltage v in 4.5 16 v input under-voltage lockout threshold v uvlo v in rising v in falling 4.0 3.7 v v supply current (quiescent) i in i out = 0, v fb = 1.2v, v en >2v 2 3 ma shutdown supply current i off v en = 0v 3 20 a feedback voltage v fb 0.782 0.8 0.818 v load regulation 0.5 % line regulation 1 % feedback voltage input current i fb 200 na en input threshold v en off threshold on threshold 2.0 0.6 v v en input hysteresis v hys 100 mv modulator frequency f o 350 500 600 khz maximum duty cycle d max 100 % minimum duty cycle d min 6 % error amplifier voltage gain 500 v/v error amplifier transconductance 200 a/v protection current limit i lim 4 5 a over-temperature shutdown limit t j rising t j falling 145 100 c c soft start interval t ss 4 ms output stage high-side switch on-resistance v in = 12v v in = 5v 40 65 50 85 m ? m ? notes: 1. exceeding the absolute maximum ratings may damage the device. 2. the device is not guaranteed to operate beyond the maximum operating ratings. 3. devices are inherently esd sensitive, handling precau tions are required. human body model rating: 1.5k ? in series with 100pf. 4. specification in bold indicate an ambient temperature range of -40c to +85c. these specifications are guaranteed by design.
^lwnmnoa april 2006 www.aosmd.com page 4 of 17 functional block diagram level shifter + fet driver 500khz oscillator uvlo & por lx fb pgnd comp en agnd + - pwm control logic + ? + isen ilimit pwm comp 5v ldo regulator + - eamp internal +5v reference & bias otp softstart 0.8v lx vin q1 d1
^lwnmnoa april 2006 www.aosmd.com page 5 of 17 typical performance characteristics circuit of figure 1. t a = 25c, v in = v en = 12v, v out = 3.3v unless otherwise specified. light load (dcm) operation vin ripple 0.1v/div vo ripple 20mv/div iin 2a/div vlx 10v/div 1us/div start up to full load vin 5v/div vo 1v/div iin 2a/div 1ms/div 50% to 100% load transient vo ripple 0.1v/div io 2a/div 100us/div full load (ccm) operation vin ripple 0.1v/div vo ripple 20mv/div iin 2a/div vlx 10v/div 1us/div full load to turn off vin 5v/div vo 1v/div iin 2a/div 1ms/div light load to turn off vin 5v/div vo 1v/div iin 2a/div 1s/div
^lwnmnoa april 2006 www.aosmd.com page 6 of 17 short circuit protection vo 2v/div il 2a/div 100us/div short circuit recovery vo 2v/div il 2a/div 1ms/div efficiency (vin=12v) vs. load current aoz1012d efficiency 75% 80% 85% 90% 95% 0 0.5 1 1.5 2 2.5 3 load current (a) eff (%) 8 v out 5 v out 3.3 v out 8.0v output 5.0v output 3.3v output
^lwnmnoa april 2006 www.aosmd.com page 7 of 17 thermal de-rating curves for dfn-8 package part under typical input and output condition circuit of figure 1. 25oc ambient temperature and natura l convection (air speed<50lfm) unless otherwise specified. AOZ1012DI de-rating curves at 5 v input derating curve at 5v input 0 0.5 1 1.5 2 2.5 3 25 35 45 55 65 75 85 ambient temperature (ta) output current (io ) 1.8v output 3.3v output 5v output 1.8v output 5.0v output 3.3v output AOZ1012DI de-rating curves at 12v input derating curve at 12v input 0 0.5 1 1.5 2 2.5 3 3.5 25 35 45 55 65 75 85 ambient temperature (ta) output current (io ) 1.8v output 3.3v output 5.0v output 8.0v output 3.3v output 5.0v output 1.8v output 8.0v output
^lwnmnoa april 2006 www.aosmd.com page 8 of 17 detailed description aoz1012d is a current-mode step down regulator with integrated high side pmos switch and a low side freewheeling schottky diode. it operates from a 4.5v to 16v input voltage range and supplies up to 3a of load current. the duty cycle can be adjusted from 6% to 100% allowing a wide range of output voltage. features include enable control, power-on reset, input under voltage lockout, fixed internal soft-start and thermal shut down. aoz1012d is available in thermally enhanced dfn-8 package. enable and soft start aoz1012d has internal soft start feature to limit in-rush current and ensure the output voltage ramps up smoothly to regulation voltage. a soft start process begins when the input voltage rises to 4.0v and voltage on en pin is high. in soft start process, the output voltage is ramped to regulation voltage in typically 4ms. the 4ms soft start time is set internally. the en pin of the aoz1012d is active high. connect the en pin to vin if enable function is not used. pull it to ground will disable the aoz1012d. do not leave it open. the voltage on en pin must be above 2.0 v to enable the aoz1012d. when voltage on en pin falls below 0.6 v, the aoz1012d is disabled. if an application circuit requires the aoz1012d to be disabled, an open drain or open collector circuit should be used to interface to en pin. steady-state operation under steady-state conditions, the converter operates in fixed frequency and continuous-conduction mode (ccm). aoz1012d integrates an internal p-mosfet as the high-side switch. inductor current is sensed by amplifying the voltage drop across the drain to source of the high side power mo sfet. output voltage is divided down by the external voltage divider at the fb pin. the difference of the fb pin voltage and reference is amplified by the internal transconductance error amplifier. the error voltag e, which shows on the comp pin, is compared against the current signal, which is sum of inductor current signal and ramp compensation signal, at pwm comparator input. if the current signal is less than the error voltage, the internal high-side switch is on. the inductor current flows from the input through the inductor to the output. when the current signal exceeds the error voltage, the high-side switch is off. the inductor current is freewheeling through the internal schottky diode to output. the aoz1012d uses a p-channel mosfet as the high side switch. it saves the bootstrap capacitor normally seen in a circuit which is using an nmos switch. it allows 100% turn-on of the upper switch to achieve linear regulation mode of operation. the minimum voltage drop from v in to v o is the load current times dc resistance of mosfet plus dc resistance of buck inductor. it can be calculated by equation below: ) ( ) ( _ inductor on ds o in max o r r i v v + ? = where v o_max is the maximum output voltage; v in is the input voltage from 4.5v to 16v; i o is the output curr ent from 0a to 3a; r ds(on) is the on resistance of internal mosfet, the value is between 40m and 85m depending on input voltage and junction temperature; r inductor is the inductor dc resistance; switching frequency the aoz1012d switching frequency is fixed and set by an internal oscillator. the actuall switching frequency could range from 350khz to 600khz due to device variation. output voltage programming output voltage can be set by feeding back the output to the fb pin with a resistor divider network. in the application circuit shown in fi gure 1. the resistor divider network includes r 1 and r 2 . usually, a design is started by picking a fixed r 2 value and calculating the required r1 with equation below. ) 1 ( 8 . 0 2 1 r r v o + = some standard value of r 1 , r 2 for most commonly used output voltage values are listed in table 1. table 1. vo (v) r1 (k ? ) r2 (k ? ) 0.8 1.0 open 1.2 4.99 10 1.5 10 11.5 1.8 12.7 10.2 2.5 21.5 10 3.3 31.6 10 5.0 52.3 10
^lwnmnoa april 2006 www.aosmd.com page 9 of 17 combination of r1 and r2 should be large enough to avoid drawing excessive current from the output, which will cause power loss. since the switch duty cycle can be as high as 100%, the maximum output voltage can be set as high as the input voltage minus the voltage drop on upper pmos and inductor. protection features aoz1012d has multiple protection features to prevent system circuit damage under abnormal conditions. over current protection (ocp) the sensed inductor current signal is also used for over current protection. since aoz1012d employs peak current mode control, the comp pin voltage is proportional to the peak inductor current. the comp pin voltage is limited to be between 0.4v and 2.5v internally. the peak inductor current is automatically limited cycle by cycle. the cycle by cycle current limit threshold is set between 4a and 5a. when the load current reaches the current limit threshold, the cycle by cycle current limit circuit turns off the high side switch immediately to terminate the current duty cycle. the inductor current stop rising. the cycle by cycle current limit protection directly limits inductor peak current. the average inductor current is also limited since the limitation of peak inductor current. when cycle by cycle current limit circuit is triggered, the output voltage drops as the duty cycle decreasing. the aoz1012d has internal short circuit protection circuit to protect itself from catastrophic failure under output short circuit conditions. the fb pin voltage is proportional to the output voltage. whenever fb pin voltage is below 0.2v, the short circuit protection circuit is triggered. as a result, the converter is shut down and hiccups at a frequency equals to 1/8 of normal switching frequency. the conv erter will start up via a soft start once the short circuit cond ition disappears. in short circuit protection mode, the inductor average current is greatly reduced because of the low hiccup frequency. power-on reset (por) a power-on reset circuit monitors the input voltage. when the input voltage exceeds 4v, the converter starts operation. when input voltage falls below 3.7v, the converter will stop switching. thermal protection an internal temperature sensor monitors the junction temperature. it shuts down the internal control circuit and high side pmos if the junction temperature exceeds 145oc. the regulato r will restart automatically under the control of soft-start circuit when the junction temperature decreases to 100oc. application information the basic aoz1012d application circuit is shown in figure 1. component selection is explained below. input capacitor the input capacitor must be connected to the v in pin and pgnd pin of aoz1012d to maintain steady input voltage and filter out the pulsing input current. the voltage rating of input capacitor must be greater than maximum input voltage plus ripple voltage. the input ripple voltage can be approximated by equation below: in o in o in o in v v v v c f i v ? = ? ) 1 ( since the input current is discontinuous in a buck converter, the current stress on the input capacitor is another concern when selecting the capacitor. for a buck circuit, the rms value of input capacitor current can be calculated by: ) 1 ( _ in o in o o rms cin v v v v i i ? = if let m equal the conversion ratio: m v v in o = the relation between the input capacitor rms current and voltage conversion ratio is calculated and shown in fig. 2 below. it can be seen that when v o is half of v in , c in is under the worst current stress. the worst current stress on c in is 0.5i o .
^lwnmnoa april 2006 www.aosmd.com page 10 of 17 0 0.5 1 0 0.1 0.2 0.3 0.4 0.5 0.5 0 i cin_rms m () i o 1 0 m figure 2. i cin vs. voltage conversion ratio for reliable operation and best performance, the input capacitors must have current rating higher than i cin-rms at worst operating conditions. ceramic capacitors are preferred for input capacitors because of their low esr and high ripple current rating. depending on the application circuits, other low esr tantalum capacitor may also be used. when selecting ceramic capacitors, x5r or x7r type dielectric ceramic capacitors are preferred for their better temperature and voltage characteristics. note that the ripple current rating from capacitor manufactures are based on certain amount of life time. further de-rating may be necessary for practical design requirement. inductor the inductor is used to supply constant current to output when it is driven by a switching voltage. for given input and output voltage, inductance and switching frequency together decide the inductor ripple current, which is, ) 1 ( in o o l v v l f v i ? = ? the peak inductor current is: 2 l o lpeak i i i ? + = high inductance gives low inductor ripple current but requires larger size inductor to avoid saturation. low ripple current reduces inductor core losses. it also reduces rms current through inductor and switches, which results in less conduc tion loss. usually, peak to peak ripple current on inductor is designed to be 20% to 30% of output current. when selecting the inductor, make sure it is able to handle the peak current without saturation even at the highest operating temperature. the inductor takes the highest current in a buck circuit. the conduction loss on inductor needs to be checked for thermal and efficiency requirements. surface mount inductors in different shape and styles are available from coilcraft, elytone and murata. shielded inductors are small and radiate less emi noise. but they cost more than unshielded inductors. the choice depends on emi requirement, price and size. table below lists some indu ctors for typical output voltage design. table 2. vout l1 manufacture shield, 5.8uh et553-5r8 elytone 5.0 v un-shielded, 4.7uh do3316p-472mld coilcraft un-shielded, 4.7uh do3316p-472mld coilcraft 3.3 v un-shielded, 4.7uh do1813p-472hc coilcraft shield, 2.2uh et553-2r2 elytone un-shielded, 2.2uh do3316p-222mld coilcraft 1.8 v un-shielded, 2.2uh do1813p-222hc coilcraft output capacitor the output capacitor is selected based on the dc output voltage rating, output ripple voltage specification and ripple current rating. the selected output capacitor must have a higher rated voltage specification than the maximum desired output voltage including ripple. de-rating needs to be considered for long term reliability. output ripple voltage specific ation is another important factor for selecting the output capacitor. in a buck converter circuit, output ripple voltage is determined by inductor value, sw itching frequency, output capacitor value and esr. it can be calculated by the equation below: ) 8 1 ( o co l o c f esr i v + ? = ?
^lwnmnoa april 2006 www.aosmd.com page 11 of 17 where c o is output capacitor value and esr co is the equivalent series resistor of output capacitor. when low esr ceramic capacitor is used as output capacitor, the impedance of the capacitor at the switching frequency dominates. output ripple is mainly caused by capacitor value an d inductor ripple current. the output ripple voltage calculation can be simplified to: o l o c f i v ? = ? 8 1 if the impedance of esr at switching frequency dominates, the output ripple voltage is mainly decided by capacitor esr and inductor ripple current. the output ripple voltage calculation can be further simplified to: co l o esr i v ? = ? for lower output ripple voltage across the entire operating temperature range, x5r or x7r dielectric type of ceramic, or other low esr tantalum are recommended to be used as output capacitors. in a buck converter, output capacitor current is continuous. the rms current of output capacitor is decided by the peak to peak inductor ripple current. it can be calculated by: 12 _ l rms co i i ? = usually, the ripple current ra ting of the output capacitor is a smaller issue because of the low current stress. when the buck inductor is selected to be very small and inductor ripple current is high, output capacitor could be overstressed. loop compensation aoz1012d employs peak curr ent mode control for easy use and fast transient response. peak current mode control eliminates the double pole effect of the output l&c filter. it greatly simp lifies the comp ensation loop design. with peak current mode control, the buck power stage can be simplified to be a one-pole and one-zero system in frequency domain. the pole is dominant pole and can be calculated by: l o p r c f = 2 1 1 the zero is a esr zero due to output capacitor and its esr. it is can be calculated by: co o z esr c f = 2 1 1 where c o is the output filter capacitor; r l is load resistor value; esr co is the equivalent series resistance of output capacitor; the compensation design is actually to shape the converter close loop transfer function to get desired gain and phase. several different types of compensation network can be used for aoz1012d. for most cases, a series capacitor and resistor network connected to the comp pin sets the pole-zero and is adequate for a stable high-bandwidth control loop. in aoz1012d, fb pin and comp pin are the inverting input and the output of internal transconductance error amplifier. a series r and c compensation network connected to comp provides one pole and one zero. the pole is: vea c ea p g c g f = 2 2 where g ea is the error amplifier transconductance, which is 200 10 -6 a/v; g vea is the error amplifier voltage gain, which is 500 v/v; c c is compensation capacitor; the zero given by the external compensation network, capacitor c c and resistor r c , is located at: c c z r c f = 2 1 2 to design the compensation circuit, a target crossover frequency f c for close loop must be selected. the system crossover frequency is where control loop has unity gain. the crossover frequency is the also called the converter bandwidth. generally a higher bandwidth means faster response to load transient. however, the bandwidth should not be too high because of system stability concern. when de signing the compensation
^lwnmnoa april 2006 www.aosmd.com page 12 of 17 loop, converter stability under all line and load condition must be considered. usually, it is recommended to set the bandwidth to be less than 1/10 of switching frequency. the aoz1012d operates at a fixed switching frequency range from 350khz to 600khz. it is recommended to choose a crossover frequency less than 30khz. khz f c 30 = the strategy for choosing r c and c c is to set the cross over frequency with r c and set the compensator zero with c c . using selected crossover frequency, f c , to calculate r c : cs ea o fb o c c g g c v v f r = 2 where f c is desired cros sover frequency; v fb is 0.8v; g ea is the error amplifier transconductance, which is 200 10 -6 a/v; g cs is the current sense circuit transconductance, which is 6.68 a/v; the compensation capacitor c c and resistor r c together make a zero. this zero is put somewhere close to the dominate pole f p1 but lower than 1/5 of selected crossover frequency. c c can is selected by: 1 2 5 . 1 p c c f r c = equation above can also be simplified to: c l o c r r c c = an easy-to-use application software which helps to design and simulate the compensation loop can be found at www.aosmd.com. thermal management and layout consideration in the aoz1012d buck regulator circuit, high pulsing current flows through two circuit loops. the first loop starts from the input capacitors, to the vin pin, to the lx pins, to the filter inductor, to the output capacitor and load, and then return to the input capacitor through ground. current flows in the first loop when the high side switch is on. the second loop starts from inductor, to the output capacitors and load, to the pgnd pin of the aoz1012d, to the lx pins of the azo1012d. current flows in the second loop when the low side diode is on. in pcb layout, minimizing the two loops area reduces the noise of this circuit and improves efficiency. a ground plane is strongly recommended to connect input capacitor, output capacitor, and pgnd pin of the aoz1012d. in the aoz1012d buck regulator circuit, the two major power dissipating components are the aoz1012d and output inductor. the total power dissipation of converter circuit can be measured by input power minus output power. o o in in total i v i v p ? ? ? = the power dissipation of inductor can be approximately calculated by output current and dcr of inductor. 1 . 1 2 ? ? = inductor o indcutor r i p the actual aoz1012d junc tion temperature can be calculated with power dissipation in the aoz1012d and thermal impedance from junction to ambient. ja inductor total junction p p t ? ? = ) ( the maximum junction temperature of aoz1012d is 150oc, which limits the maximum load current capability. please see the thermal de-rating curves for the maximum load current of the aoz1012d under different ambient temperature. the thermal performance of aoz1012d is strongly affected by the pcb layout. extra care should be taken by users during design process to ensure that the ic will operate under the recommended environmental conditions. several layout tips are listed below for the best electric and thermal performance. the figure 3 below illustrates a pcb layout example as reference. 1. do not use thermal relief connection to the vin and the pgnd pin. pour a maximized copper area to the pgnd pin and the vin pin to help thermal dissipation.
^lwnmnoa april 2006 www.aosmd.com page 13 of 17 2. input capacitor should be connected to the vin pin and the pgnd pin as close as possible. 3. a ground plane is preferred. if a ground plane is not used, separate pgnd from agnd and connect them only at one point to avoid the pgnd pin noise coupling to the agnd pin. 4. make the current trace from lx pins to l to co to the pgnd as short as possible. 5. pour copper plane on all unused board area and connect it to stable dc nodes, like vin, gnd or vout. 6. the two lx pins are connected to internal pfet drain. they are low resistance thermal conduction path and most noisy switching node. connected a copper plane to lx pin to help thermal dissipation. this copper plane should not be too larger otherwise switching noise may be coupled to ot her part of circuit. lx lx vin pg ag fb en cp cin l cout thermal pad: lx thermal pad: agnd via to ground plane vin vo gnd figure 3. aoz1012d pcb layout
^lwnmnoa april 2006 www.aosmd.com page 14 of 17 dfn-8 package marking description z1012di faywlt note: logo aos logo z1012di part number code f&a fab & assembly location y year code w week code l&t assembly lot code
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